Moved fb interrupt handling related code to fb intr sub-unit.
Moved following hals from fb hal to fb intr hal and renamed to:
void (*enable)(struct gk20a *g);
void (*disable)(struct gk20a *g);
void (*isr)(struct gk20a *g);
gk20a_readl/writel are replaced with nvgpu_read/writel.
Hals are populated with new function names and code is modified
to call new hals.
Moved ecc interrupt to gv11b_fb_intr_handle_ecc in a separate file:
fb_intr_ecc_gv11b.c/h
JIRA NVGPU-2034
Change-Id: I80c7110c902c4e082561cf7cbe65c20eb9acb661
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090070
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a) free_channel_ctx_header is used to free the channel's underlying subctx
and belongs to the hal.channel unit instead of fifo. Moved the same and
renamed the HAL ops to free_ctx_header. The function
gv11b_free_subctx_header is moved to channel_gv11b.* files and also
renamed to gv11b_channel_free_subctx_header.
b) ch_abort_clean_up is moved to hal.channel unit
c) channel_resume and channel_suspend are used to resume and suspend all
the serviceable channels. This belongs to hal.channel unit and are
moved from the hal.fifo unit.
The HAL ops channel_resume and channel_suspend are renamed to
resume_all_serviceable_ch and suspend_all_serviceable_ch respectively.
gk20a_channel_resume and gk20a_channel_suspend are also renamed to
nvgpu_channel_resume_all_serviceable_ch and
nvgpu_channel_suspend_all_serviceable_ch respectively.
d) set_error_notifier HAL ops belongs to hal.channel and is moved
accordingly.
Jira NVGPU-2978
Change-Id: Icb52245cacba3004e2fd32519029a1acff60c23c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083593
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- Enable the reporting of PFIFO related errors such as engine syncpoint error,
memop timeout error, lb error to 3LSS framework.
- Remove the reporting of bind_error from gk20a since we already report it
from gv11b related fifo hal file.
Jira NVGPU-3087
Change-Id: Ic002be3a12a049010165870b861cdfb13a7f33d8
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088579
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Add new hal handle_exceptions in hal.gr.intr
This hal handles all the gr exceptions which involves register read and
write.To keep the code simple, handle gpc_exception outside this hal
as gpc exception involves common intr function call and variables
not needed by other exceptions.
JIRA NVGPU-3016
Change-Id: Ie1fb60e46419ee20a10ac9cfb4874cb6eb3739b9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090406
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Added the following HALs
- ramin.base_shift
- ramin.alloc_base
Use above HALs in mm, instead of using hw definitions.
Defined nvgpu_inst_block_ptr to
- get inst_block address,
- shift if by base_shift
- assert upper 32 bits are 0
- return lower 32 bits
Added missing #include for <nvgpu/mm.h>
Jira NVGPU-3015
Change-Id: I558a6f4c9fbc6873a5b71f1557ea9ad8eae2778f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077840
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Moved fecs_host_int_enable ops from gr to gr falcon.
Created required hals in gm20b and gv11b gr falcon units.
gr_gk20a_fecs_host_int_enable -> gm20b_gr_falcon_fecs_host_int_enable
gr_gv11b_fecs_host_int_enable -> gv11b_gr_falcon_fecs_host_int_enable
JIRA NVGPU-1881
Change-Id: Ice9d5170928068b0447cc4644e6668f7ff75b8d6
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089316
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Moved following functionality from gr to gr falcon common
gr_gk20a_init_ctxsw -> nvgpu_gr_falcon_init_ctxsw
gr_gk20a_init_ctx_state -> nvgpu_gr_falcon_init_ctx_state
gk20a_init_gr_bind_fecs_elpg -> nvgpu_gr_falcon_bind_fecs_elpg
Replaced code in gr_gk20a.c by calling corresponding gr falcon common
calls and moved all relevant code to gr falcon unit.
Moved following gr ops from gr to gr falcon:
int (*init_ctx_state)(struct gk20a *g);
Moved functionality from gr to relevant gr falcon hals:
gr_gk20a_init_ctx_state -> gm20b_gr_falcon_init_ctx_state
gr_gp10b_init_ctx_state -> gp10b_gr_falcon_init_ctx_state
JIRA NVGPU-1881
Change-Id: I027e1972a7747275311df99679235804dc0e16fe
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084391
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Move all fecs methods related code to gr falcon unit and handle it
through generic gr.falocn.ctrl_ctxsw hal.
Following methods are moved from gr_gk20a.c to gr falcon unit.
fecs method and corresponding new fecs method def in gr_falcon.h:
gr_fecs_method_push_adr_discover_image_size_v ->
NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_IMAGE_SIZE
gr_fecs_method_push_adr_discover_pm_image_size_v ->
NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_PM_IMAGE_SIZE
gr_fecs_method_push_adr_discover_reglist_image_size_v ->
NVGPU_GR_FALCON_METHOD_REGLIST_DISCOVER_IMAGE_SIZE
gr_fecs_method_push_adr_set_reglist_bind_instance_v ->
NVGPU_GR_FALCON_METHOD_REGLIST_BIND_INSTANCE
gr_fecs_method_push_adr_set_reglist_virtual_address_v ->
NVGPU_GR_FALCON_METHOD_REGLIST_SET_VIRTUAL_ADDRESS
Following fecs methods are moved from obj_ctx.c to gr falcon unit.
gr_fecs_method_push_adr_bind_pointer_v ->
NVGPU_GR_FALCON_METHOD_ADDRESS_BIND_PTR
gr_fecs_method_push_adr_wfi_golden_save_v ->
NVGPU_GR_FALCON_METHOD_GOLDEN_IMAGE_SAVE
Following fecs methods are moved from gr_gp10b.c to gr falcon unit.
gr_fecs_method_push_adr_discover_preemption_image_size_v ->
NVGPU_GR_FALCON_METHOD_PREEMPT_IMAGE_SIZE
gr_fecs_method_push_adr_configure_interrupt_completion_option_v ->
NVGPU_GR_FALCON_METHOD_CONFIGURE_CTXSW_INTR
Following fecs method is moved from zcull_gm20b.c:
gr_fecs_method_push_adr_discover_zcull_image_size_v ->
NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_ZCULL_IMAGE_SIZE
Following fecs method is moved from fecs_trace_gp10b.c:
gr_fecs_method_push_adr_write_timestamp_record_v
-> NVGPU_GR_FALCON_METHOD_FECS_TRACE_FLUSH
Added new HAL in gr falcon for moving fecs_current_ctx_data from
gr_gk20a.c to gr_falcon_gm20b.c.
u32 (*get_fecs_current_ctx_data)(struct gk20a *g,
struct nvgpu_mem *inst_block);
Added overlay for gm20b_gr_falcon_ctrl_ctxsw in newly added in
gr_falcon_gp10b.c for handling gp10b+ specific fecs methods:
gp10b_gr_falcon_ctrl_ctxsw
JIRA NVGPU-1881
Change-Id: I662d06f5176b29e6837d63c25e42de67505d48f5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087148
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PMU mutexes used by FIFO and runlists is functionality independent of
the PMU command and message management.
Remove related functionality from pmu_ipc.c and prepare pmu_mutex.c.
Prepare PMU HAL unit that contains gk20a specific PMU mutexes
handling.
JIRA NVGPU-1970
Change-Id: I0204be2ef9d2c000004667af3c18dc527d7ac25f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079142
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New tpc_exception_sm_disable hal to disable and
tpc_exception_sm_enable hal to enable the sm bit in tpc_exception
register.
These hals are added to avoid the register access in common gr code.
JIRA NVGPU-3016
Change-Id: I21634e2cd3b2b8007081e6f7608ec2da9c74813f
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088311
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- Enable the reporting of PRI access violation.
- While enabling PRI access violation, it has been found that PRI timeout
reporting was added part of ptimer. Since both PRI timeout and access
violation are logically co-related, we have decided to add them as part
of PRIV_RING.
Jira NVGPU-3087
Change-Id: I5543f1b5d0ab01354ffff16c172a635b2df1fd26
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087824
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Move init_ce_engine_info from fifo to hal/engine unit as
implementation is chip specific.
Rename init_ce_engine_info to init_ce_info
Rename gp10b_fifo_init_ce_engine_info to gp10b_engine_init_ce_info
Rename gm20b_fifo_init_ce_engine_info to gm20b_engine_init_ce_info
JIRA NVGPU-1313
Change-Id: Idb9ba3f2550eff6bbe7163d12e48086f47d3f319
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085427
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Added following new hals in gr falcon:
u32 (*get_current_ctx)(struct gk20a *g);
-> to get current context in execution.
u32 (*get_ctx_ptr)(u32 ctx);
-> related ctx_ptr for the context
Updated gr_gk20a.c, gr_gm20b.c, gr_gp10b.c and gr_gv11b.c
to use these new hals.
JIRA NVGPU-1881
Change-Id: I1c1cef8e4b0ca04e3e3218d552b6e8e08fcfa7d0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087039
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Change gk20a_gr_nonstall_isr function to hal under hal.gr.intr
Use nvgpu_gr_gpc_offset and nvgpu_gr_tpc_offset call in
gm20b_gr_intr_handle_tex_exception function.
Update gk20a_gr_nonstall_isr call as g->ops.gr.intr.nonstall_isr
JIRA NVGPU-3016
Change-Id: I9ff39cf1a99bf5b3d215cda6bc68fab1ecae51e3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088133
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Move handle_gcc_exception to hal.gr.intr
Pass g->ecc.gr.gpccs_ecc_corrected_err_count[gpc].counter and
g->ecc.gr.gpccs_ecc_uncorrected_err_count[gpc].counter variable pointers
as function parameter to avoid dereferencing the g->ecc struct
inside the hal function
Update g->ops.gr.handle_gcc_exception to
g->ops.gr.intr.handle_gcc_exception
JIRA NVGPU-3016
Change-Id: Iaac9bd1763673567d8c29258d2f1952d061785a6
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087199
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Move handle_gpc_gpcmmu_exception to hal.gr.intr
Pass g->ecc.gr.mmu_l1tlb_ecc_corrected_err_count[gpc].counter
and g->ecc.gr.mmu_l1tlb_ecc_uncorrected_err_count[gpc].counter pointers
as function parameter to avoid dereferencing g->ecc inside hal function
Update g->ops.gr.handle_gpc_gpcmmu_exception to
g->ops.gr.intr.handle_gpc_gpcmmu_exception
JIRA NVGPU-3016
Change-Id: I9698cf71b568caf8e259996f84b4f26aded865f5
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087198
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Moved below hals from {chip}/fifo_{chip}.[ch] to hal/fifo
get_mmu_fault_info
get_mmu_fault_desc
get_mmu_fault_client_desc
get_mmu_fault_gpc_desc
Moved gk20a_fifo_handle_dropped_mmu_fault to hal/fifo
JIRA NVGPU-1313
Change-Id: I949bcd482156c6e381006387372f13770277e8c5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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Following functions are moved from gr_gk20a.c to common gr_falcon.c
gr_gk20a_disable_ctxsw -> nvgpu_gr_falcon_disable_ctxsw
gr_gk20a_enable_ctxsw -> nvgpu_gr_falcon_enable_ctxsw
gr_gk20a_halt_pipe -> nvgpu_gr_falcon_halt_pipe
Added new gr falcon hal to control ctxsw:
int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method,
u32 data, u32 *ret_val)
Parameters:
fecs_method: will be specified by a generic define provided in gr_falcon.h
header.
data: input data parameter (if any), set it to zero, if method did not
require any data input.
ret_val: pointer to expected output.
Added following ops for gr falcon:
int (*halt_pipe)(struct gk20a *g); -> this is moved from gr
int (*disable_ctxsw)(struct gk20a *g);
int (*enable_ctxsw)(struct gk20a *g);
JIRA NVGPU-1881
Change-Id: Idb3b7355b5a0bd3b9bb01f9f424c5d607616f540
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081308
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Move handle_gpc_gpccs_exception hal to hal.gr.intr
Pass g->ecc.gr.gpccs_ecc_corrected_err_count[gpc].counter and
g->ecc.gr.gpccs_ecc_uncorrected_err_count[gpc].counter variable address
as parameter to function to avoid dereferencing g->ecc variable
inside hal function.
Update g->ops.gr.handle_gpc_gpcss_exception call to
g->ops.gr.intr.handle_gpc_gpcss_exception
JIRA NVGPU-3016
Change-Id: I6cab6428eb6785261f34ca21f2ce055a9995b408
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087197
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Add new hal to get_tpc_exception to hal.gr.intr
This hal helps to avoid register read from the
common handle_tpc_exception function. Add a new struct to report the
tpc_exception type back to the common code to handle the exception.
JIRA NVGPU-3016
Change-Id: Ib504ade0b06b85cd38ccf166328784bab072573e
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085387
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Move chip specific mc code from common/mc to hal/mc.
Replace gk20a_readl/writel with nvgpu_readl/writel
Replace 0xFFFFFFFFU with U32_MAX hash define
Change local variable names to fix checkpatch errors/warnings
Change BUG to WARN
Move defines to header files
Create new defines for hard coded delays
JIRA NVGPU-2041
Change-Id: I3594121a81da37ef58c47e87c45e96441e4cf8c7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085268
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Add new unit common.gr.setup that provides runtime setup interfaces to
other units outside of GR unit or to OS-specific code
Move zcull setup call to this unit.
New unit now exposes nvgpu_gr_setup_bind_ctxsw_zcull() to setup zcull
This API internally calls common.gr.zcull API nvgpu_gr_zcull_ctx_setup()
Add new hal g->ops.gr.setup.bind_ctxsw_zcull() and remove
g->ops.gr.zcull.bind_ctxsw_zcull()
Remove nvgpu_channel_gr_zcull_setup() from channel unit
Also remove ctx/subctx header includes sicne channel code need not
configure zcull
Remove gm20b_gr_bind_ctxsw_zcull() since binding is done from common
code
Jira NVGPU-1886
Change-Id: I6f04d19a8b8c003734702c5f6780a03ffc89b717
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2086602
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In this CL, following ctxsw related code is moved to hal gr falcon.
1. gr_gk20a_wait_ctxsw_ready -> gm20b_gr_falcon_wait_ctxsw_ready
2. gr_gk20a_submit_fecs_method_op ->
gm20b_gr_falcon_submit_fecs_method_op
3. gr_gk20a_submit_fecs_sideband_method_op->
gm20b_gr_falcon_submit_fecs_sideband_method_op
Above functions are populated with following gr.falcon hals and called
from the current code as required:
int (*wait_ctxsw_ready)(struct gk20a *g);
int (*submit_fecs_method_op)(struct gk20a *g,
struct fecs_method_op_gk20a op, bool sleepduringwait);
int (*submit_fecs_sideband_method_op)(struct gk20a *g,
struct fecs_method_op_gk20a op);
Following static function also moved to gr_gk20a.c to hal gr falcon.
gr_gk20a_ctx_wait_ucode -> gm20b_gr_falcon_ctx_wait_ucode
JIRA NVGPU-1881
Change-Id: Icb4238dcacaf46ecfcada8bc8dcdeb68b6278bab
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085189
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Remove locally defined timeout call in gr and use common timeout
call.
Replace nvgpu_gr_get_idle_timeout with nvgpu_get_poll_timeout function
Replace following defines to
NVGPU_GR_IDLE_CHECK_DEFAULT_US ---> POLL_DELAY_MIN_US
NVGPU_GR_IDLE_CHECK_MAX_US ---> POLL_DELAY_MIN_US
JIRA NVGPU-1885
Change-Id: I4514a9763fe0687680d50704bc9f22677a1a3df9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085031
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Add new hal g->ops.gr.falcon.set_current_ctx_invalid() in hal.gr.falcon
unit to invalidate current_ctx by setting invalid flag in register
gr_fecs_current_ctx_r()
Use new hal in gr_gk20a_init_golden_ctx_image() instead of accessing the
register directly
Define the hal for all supported chips
Jira NVGPU-2961
Change-Id: I756dac505c661ea2754abdbf6934927d1b469be3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085032
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Add new hal g->ops.gr.init.gfxp_wfi_timeout() in hal.gr.init unit
to commit gfxp timeout
Define gv11b chip specific operation
Use new hal in gr_gv11b_update_ctxsw_preemption_mode() instead of
directly committing using register accessors
Jira NVGPU-2961
Change-Id: I7694e3128920d9a2856faecf2e3d10a11f0f986e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084750
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Add new hal g->ops.gr.init.commit_cbes_reserve() in hal.gr.init unit
to commit cbes reserve
Define gp10b and gv11b chip specific operations
Use new hals in gr_gp10b_update_ctxsw_preemption_mode() and
gr_gv11b_update_ctxsw_preemption_mode() instead of directly committing
using register accessors
Jira NVGPU-2961
Change-Id: Iea2032ea61264c286b1fab46435ff5a84c90d3da
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084749
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Add new hal g->ops.gr.init.commit_ctxsw_spill() in hal.gr.init unit
to commit spill ctxsw buffer
Define gp10b and gv11b operations
Use new hals in gr_gp10b_update_ctxsw_preemption_mode() and
gr_gv11b_update_ctxsw_preemption_mode() instead of directly committing
using register accessors
Jira NVGPU-2961
Change-Id: Iced02d304f12bcb4e78ea31a7728baa04081e325
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084748
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below hals are used to get preemption buffer sizes
g->ops.gr.get_ctx_spill_size()
g->ops.gr.get_ctx_pagepool_size()
g->ops.gr.get_ctx_betacb_size()
g->ops.gr.get_ctx_attrib_cb_size()
Move them to hal.gr.init unit
Copy over corresponding gp10b/gv11b definitions
Remove pagepool and attrib_cb size hals from gv11b since gv11b can
re-use gp10b hals
Add spill size and betacb size hals for gv100 and tu104 too since
register values are different on those chips
Remove g->ops.gr.init_gfxp_rtv_cb() hal and replace it by
g->ops.gr.init.get_gfxp_rtv_cb_size() which returns the size of RTV
cb size
Jira NVGPU-2961
Change-Id: I3f2f973c120dbfd22067366f87d06b5c9162defb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084747
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Moved enable/disable HALs from fifo to tsg:
- tsg.enable
- tsg.disable
gk20a_tsg_enable and gv11b_tsg_enable are moved to HAL,
since they are chip specific, even though they do not
directly access chip registers.
Removed vgpu_gv11b_tsg_enable as it was identical to
gv11b_tsg_enable.
Changed gv11b_fifo_locked_abort_runlist_active_tsgs and
gv11b_fifo_teardown_ch_tsg to use tsg.enable HAL instead
of calling directly gk20a_disable_tsg HAL implementation.
Jira NVGPU-2979
Change-Id: I721650c64dcf8cd158652e362292af45df43819f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083156
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Move handle_tex_exception hal function to hal.gr.intr
Move hal function for gm20b and gp10b chips.
Removed the null implementation in gv11b hal.
Modify ops->gr.handle_tex_exception call to
ops->gr.intr.handle_tex_exception
JIRA NVGPU-3016
Change-Id: Ifd88ab6f35301525f7a58e8ccf2f4796dda640bf
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084387
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
