Currently, function nvgpu_bitmap_allocator_init() initializes bitmap
with length=0 but will fail in alloc(). Function alloc() allocates
len=0 bitmap and next request also starts from same address. However,
rbtree only holds zero length allocation.
This patch adds length = 0 check in nvgpu_bitmap_allocator_init() and
alloc() functions.
JIRA NVGPU-3086
Change-Id: I0936977cd193f3eba00bba28edae257e40af23bf
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087077
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Move handle_gcc_exception to hal.gr.intr
Pass g->ecc.gr.gpccs_ecc_corrected_err_count[gpc].counter and
g->ecc.gr.gpccs_ecc_uncorrected_err_count[gpc].counter variable pointers
as function parameter to avoid dereferencing the g->ecc struct
inside the hal function
Update g->ops.gr.handle_gcc_exception to
g->ops.gr.intr.handle_gcc_exception
JIRA NVGPU-3016
Change-Id: Iaac9bd1763673567d8c29258d2f1952d061785a6
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087199
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Move handle_gpc_gpcmmu_exception to hal.gr.intr
Pass g->ecc.gr.mmu_l1tlb_ecc_corrected_err_count[gpc].counter
and g->ecc.gr.mmu_l1tlb_ecc_uncorrected_err_count[gpc].counter pointers
as function parameter to avoid dereferencing g->ecc inside hal function
Update g->ops.gr.handle_gpc_gpcmmu_exception to
g->ops.gr.intr.handle_gpc_gpcmmu_exception
JIRA NVGPU-3016
Change-Id: I9698cf71b568caf8e259996f84b4f26aded865f5
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087198
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Moved below hals from {chip}/fifo_{chip}.[ch] to hal/fifo
get_mmu_fault_info
get_mmu_fault_desc
get_mmu_fault_client_desc
get_mmu_fault_gpc_desc
Moved gk20a_fifo_handle_dropped_mmu_fault to hal/fifo
JIRA NVGPU-1313
Change-Id: I949bcd482156c6e381006387372f13770277e8c5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083287
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gr_gk20a_commit_global_ctx_buffers() is h/w independent, hence move it
to common unit common.gr.obj_ctx and rename it as
nvgpu_gr_obj_ctx_commit_global_ctx_buffers()
Delete g->ops.gr.commit_global_ctx_buffers hal
Jira NVGPU-1887
Change-Id: If1c840237b8ba2c13bed40a4315810073756aeb9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088506
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Following functions are moved from gr_gk20a.c to common gr_falcon.c
gr_gk20a_disable_ctxsw -> nvgpu_gr_falcon_disable_ctxsw
gr_gk20a_enable_ctxsw -> nvgpu_gr_falcon_enable_ctxsw
gr_gk20a_halt_pipe -> nvgpu_gr_falcon_halt_pipe
Added new gr falcon hal to control ctxsw:
int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method,
u32 data, u32 *ret_val)
Parameters:
fecs_method: will be specified by a generic define provided in gr_falcon.h
header.
data: input data parameter (if any), set it to zero, if method did not
require any data input.
ret_val: pointer to expected output.
Added following ops for gr falcon:
int (*halt_pipe)(struct gk20a *g); -> this is moved from gr
int (*disable_ctxsw)(struct gk20a *g);
int (*enable_ctxsw)(struct gk20a *g);
JIRA NVGPU-1881
Change-Id: Idb3b7355b5a0bd3b9bb01f9f424c5d607616f540
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081308
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Move handle_gpc_gpccs_exception hal to hal.gr.intr
Pass g->ecc.gr.gpccs_ecc_corrected_err_count[gpc].counter and
g->ecc.gr.gpccs_ecc_uncorrected_err_count[gpc].counter variable address
as parameter to function to avoid dereferencing g->ecc variable
inside hal function.
Update g->ops.gr.handle_gpc_gpcss_exception call to
g->ops.gr.intr.handle_gpc_gpcss_exception
JIRA NVGPU-3016
Change-Id: I6cab6428eb6785261f34ca21f2ce055a9995b408
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087197
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Add new hal to get_tpc_exception to hal.gr.intr
This hal helps to avoid register read from the
common handle_tpc_exception function. Add a new struct to report the
tpc_exception type back to the common code to handle the exception.
JIRA NVGPU-3016
Change-Id: Ib504ade0b06b85cd38ccf166328784bab072573e
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085387
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With hw minimal headers, lot of unwanted hw registers are stripped.
SW needed few updates to use minimal headers:
1. Use stride value to get non zero instance offset:
gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r() =
gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r() +
nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
gr_pri_be1_becs_be_activity0_r() = gr_pri_be0_becs_be_activity0_r() +
nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE);
2. Broadcast registers should not be used for reading status and they should be
used only for broadcast register writes. Removed following register reads
from gm20b register dump:
NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0
NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0
JIRA NVGPU-2917
Change-Id: Ie1359699136c16b67121038024c2318ddd06190c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087231
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add a new unit common.gr.obj_ctx which allocates and initializes GR
context. This unit also takes care of creating global golden image
used to initialize every context.
Add private header obj_ctx_priv.h that defines struct
nvgpu_gr_obj_ctx_golden_image
Add public header obj_ctx.h that exposes functions supported by new unit
This unit now exposes below API to allocate and initialize context
nvgpu_gr_obj_ctx_alloc()
Remove below functions from gk20a/gr_gk20a.c and move them to new unit
with below renames
gr_gk20a_fecs_ctx_bind_channel() -> nvgpu_gr_obj_ctx_bind_channel()
gr_gk20a_fecs_ctx_image_save() -> nvgpu_gr_obj_ctx_image_save()
gk20a_init_sw_bundle() -> nvgpu_gr_obj_ctx_alloc_sw_bundle()
gr_gk20a_alloc_gr_ctx() -> nvgpu_gr_obj_ctx_gr_ctx_alloc()
gr_gk20a_init_golden_ctx_image() ->
nvgpu_gr_obj_ctx_alloc_golden_ctx_image()
Use new APIs in gk20a_alloc_obj_ctx() to allocate context
For now this unit includes <nvgpu/gr/gr.h> and some h/w headers.
But they will be removed in follow up patches
Jira NVGPU-1887
Change-Id: Ib95ec1c19c5b74810f85c2feed8fdd63889d3d22
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087662
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move nvgpu_gr_wait_initialized to a gr.init hal function.
Move to hal function to avoid circular dependencies of headers.
Update nvgpu_gr_wait_initialized call to
g->ops.gr.init.wait_initialized
JIRA NVGPU-3016
Change-Id: Ia2e5f78da8528c76a8d08512151483579f250676
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085740
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Move chip specific mc code from common/mc to hal/mc.
Replace gk20a_readl/writel with nvgpu_readl/writel
Replace 0xFFFFFFFFU with U32_MAX hash define
Change local variable names to fix checkpatch errors/warnings
Change BUG to WARN
Move defines to header files
Create new defines for hard coded delays
JIRA NVGPU-2041
Change-Id: I3594121a81da37ef58c47e87c45e96441e4cf8c7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085268
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The exec_regops() API was using a u64 for the num_ops parameter. The
lower level APIs used by exec_regops() expect u32s for this value.
Update the interface to use u32.
This eliminates MISRA Rule 10.3 violations for assignment of objects of
different essential or narrower types.
JIRA: NVGPU-3023
Change-Id: I5a2a22916f81d8b3d882d224d07eedffcde1e3ee
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084207
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Add missing registers and fields related to ECC Corrected/Uncorrected
errors for gv11b. In particular, add ECC Control register and missing
fields for GR, LTC, PMU and FB, in gv11b.
Jira NVGPU-2520
Change-Id: Ic5d2201c6a7383da8151c1ba6ed83aa0743319f6
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070666
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Add new unit common.gr.setup that provides runtime setup interfaces to
other units outside of GR unit or to OS-specific code
Move zcull setup call to this unit.
New unit now exposes nvgpu_gr_setup_bind_ctxsw_zcull() to setup zcull
This API internally calls common.gr.zcull API nvgpu_gr_zcull_ctx_setup()
Add new hal g->ops.gr.setup.bind_ctxsw_zcull() and remove
g->ops.gr.zcull.bind_ctxsw_zcull()
Remove nvgpu_channel_gr_zcull_setup() from channel unit
Also remove ctx/subctx header includes sicne channel code need not
configure zcull
Remove gm20b_gr_bind_ctxsw_zcull() since binding is done from common
code
Jira NVGPU-1886
Change-Id: I6f04d19a8b8c003734702c5f6780a03ffc89b717
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2086602
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