- Added version and reseved elements in
nv_pmu_clk_clk_vin_device_boardobjgrp_set_header struct.
- Added volt_rail_idx, por_override_mode and override_mode
elements are added in nv_pmu_clk_clk_vin_device_boardobj_set
struct.
- Implemented parsing the above elements from vbios table.
- Moved from cmd to rpc in vin_load function.
- Changed the global macros of clk domain which matches to
PMU firmware for easy reference.
NVGPU-3743
Change-Id: I0189548fce19d65193203fbf6317c4a04147bf5a
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2163135
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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-dGPU PMU init message interface updated to support RPC style init
PMU init message changed to RPC event & made needed changes to
handle RPC event during init stage
-Added new RPC header PMU_RM_RPC_HEADER, header from PMU to NvGPU
which will be part of RPC events received from PMU.
-GID info moved to super-surface for dGPU, so removed GID info
fetch from DMEM for dGPU & kept support for iGPU only.
-PMU_UNIT_INIT value for dGPU init changed
JIRA NVGPU-3723
Change-Id: I016bd1150494007a56905db23b4769e693ecd5da
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153141
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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-Message header is added as part of FB message queue to have
sequence number & checksum to perform sanity check on
received message.
-Made required changes in structs to read message correctly
from data member offset but skipped to handle sanity checks
in code as NvGPU not needed for current supported messages .
-Added support to handle cmd/msg queue element changes.
JIRA NVGPU-3724
Change-Id: I85dccfab8902cbf71752582666931f482c3ec408
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155165
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Reduce code complexity of following functions in common.gr.intr
nvgpu_gr_intr_stall_isr(complexity : 33)
nvgpu_gr_intr_handle_sm_exception(complexity : 17)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create five sub functions from nvgpu_gr_intr_stall_isr function.
Four of the sub functions based interrupt types.
One sub function for getting the channel information from context
gr_intr_get_channel_from_ctx(complexity : 4)
gr_intr_handle_exception_interrupts(complexity : 11)
This function complexity will reduce with NVGPU_DEBUGGER disable
gr_intr_handle_illegal_interrupts(complexity : 5)
gr_intr_handle_error_interrupts(complexity : 7)
gr_intr_handle_pending_interrupts(complexity : 3)
and reduce nvgpu_gr_intr_stall_isr complexity to 9
Create one sub functions from nvgpu_gr_intr_handle_sm_exception function
One sub function to report back any warp error.
gr_intr_report_warp_error(with complexity : 3)
and reduce nvgpu_gr_intr_handle_sm_exception complexity to 15
This function complexity will reduce with NVGPU_DEBUGGER disable
Jira NVGPU-3662
Change-Id: Ib325d9d8bca6b48766bc8a75f428dceeac495850
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2160578
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This patch adds the support to handle and report graphics related
exceptions to 3LSS. Specifically, it adds the following exceptions:
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_CROP
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_ZROP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PROP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZCULL
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_SETUP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES0
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES1
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_PE
JIRA NVGPU-3457
Change-Id: Ib24b67ed33ae139317ec85bba3fbb80ba51fd384
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158609
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This patch reverts the following commit 13a7ef2cc7
The bios devinit for tu104 encountered the unaligned buffer scenario.
However bios devinit functionality is now removed from nvgpu. Other
than that there are no firmwares where we expect the input/output
buffer addresses to be un-aligned, hence removing the logic added
to handle un-aligned addresses.
JIRA NVGPU-3271
Change-Id: Ifd24cc5b50b9d2548878436befb2220e7bf02ed4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2161735
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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The following DEVCTLs not needed in safety build
Compiled out below DEVCTLs for safety build
* NVGPU_GPU_DEVCTL_SET_THERM_ALERT_LIMIT
* NVGPU_GPU_DEVCTL_GET_TPC_EXCEPTION_EN_STATUS
* NVGPU_GPU_DEVCTL_GET_CPU_TIME_CORRELATION_INFO
Also added config flag CONFIG_NVGPU_IOCTL_NON_FUSA
JIRA NVGPU-3768
Change-Id: Ia233d0aac8201268524581f588d97390a913ab9c
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159398
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Initialize the clock counters for GPCCLK, XBARCLK, SYSCLK.
This INIT was done in PMU before, but now disabled from TU10A profile.
Hence the initialization is moved into nvgpu.
This patch does the following.
1. Move clock files from GV100 to TU104.
2. Add the Counter HW Registers.
3. Initialize the counter registers for gpc, xbar and sysclk.
4. Change the debug fs node from gv100 to tu104.
5. Update in yaml file with new file names.
Bug 200536091
Change-Id: I436019a18f5c4c73979977666d0c04ce4c569047
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155298
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This change switches nvgpu_timeout_peek_expired() to return a bool
instead of an int to remove advisory rule MISRA 10.5 violations.
MISRA 10.5 states that the value of an expression should not be
cast to an inappropriate essential type.
JIRA NVGPU-3798
Change-Id: I5cf9badaf07493e11a639e47ae4cf221700134ff
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155617
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There was a name clash between the nvgpu_set_error_notifier*() APIs and
the SET_ERROR_NOTIFIER IOCTL. Therefore, the APIs were renamed from
nvgpu_set_error_notifier*() to nvgpu_set_err_notifier*(). This rename
was done to fix MISRA 5.x errors.
JIRA NVGPU-1633
Change-Id: I06af551a664b0706f106e853f1ea8733894f11bd
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159813
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This change switches nvgpu_nvhost_syncpt_is_expired_ext()
to return a bool instead of an int to remove advisory rule
MISRA 10.5 violations.
MISRA 10.5 states that the value of an expression should not be
cast to an inappropriate essential type.
JIRA NVGPU-3798
Change-Id: Ie0772ac7167a3c999129de0dc7f22cd96faa28fc
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159801
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
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INT-30 requires checking for overflow of arithmetic operations on
unsigned integers.
INT-31 requires bounds checking for unsigned integers cast to
smaller size.
Fix these violations by using the safe ops in nvgpu.common.mm.mm and
nvgpu.hal.mm.mm.
JIRA NVGPU-3848
Change-Id: I2751a14fb1f45d330a92040ac3c7777c52ae9199
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158860
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Reduce code complexity of following functions in gr.ecc unit
gp10b_ecc_init(complexity : 17)
gp10b_ecc_detect_enabled_units(complexity : 15)
gv11b_ecc_init(complexity : 23)
gv11b_ecc_detect_enabled_units(complexity : 30)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create four sub functions from gp10b_ecc_init function for
sub units init.
gp10b_ecc_init_lts(complexity : 2)
gp10b_ecc_init_tpc(complexity : 2)
gp10b_ecc_init_tpc_tex(complexity : 8)
gp10b_ecc_init_tpc_sm(complexity : 5)
and reduce gp10b_ecc_init complexity to 3
Create four sub functions from gp10b_ecc_detect_enabled_units function
gp10b_ecc_enable_ltc(with complexity : 4)
gp10b_ecc_enable_tex(with complexity : 4)
gp10b_ecc_enable_smshm(with complexity : 4)
gp10b_ecc_enable_smlrf(with complexity : 4)
and reduce gp10b_ecc_detect_enabled_units complexity to 3
Create four sub functions from gv11b_ecc_init function for
sub units init.
gv11b_ecc_init_tpc(complexity : 10)
gv11b_ecc_init_gpc(complexity : 6)
gv11b_ecc_init_fb(complexity : 6)
gv11b_ecc_init_other_units(complexity : 6)
and reduce gv11b_ecc_init complexity to 5
Create six sub functions from gv11b_ecc_detect_enabled_units function
gv11b_ecc_enable_smlrf(with complexity : 4)
gv11b_ecc_enable_sml1data(with complexity : 4)
gv11b_ecc_enable_sml1tag(with complexity : 4)
gv11b_ecc_enable_smicache(with complexity : 6)
gv11b_ecc_enable_ltc(with complexity : 4)
gv11b_ecc_enable_smcbu(with complexity : 4)
and reduce gv11b_ecc_detect_enabled_units complexity to 3
Jira NVGPU-3662
Change-Id: Id10be4f9a500c300f66756ebae41bfff3b734aea
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159050
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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MISRA Advisory Rule 12.3 states that the comma operator should
not be used.
This change fixes several violations of this rule in gr falcon
code.
The remaining violations of this advisory rule will be covered
in a rule-specific deviation record.
JIRA NVGPU-3798
Change-Id: Iea579356ac1da03c6730f738f5316b57e26afa7c
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155616
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Following common and corresponding hal functions are non-safe. They are
either required for intr handling or for debug. Compile them out for
igpu safety release. Moved corresponding HALs to falcon_gk20a.c.
nvgpu_falcon_copy_from_emem
nvgpu_falcon_copy_to_emem
nvgpu_falcon_clear_halt_intr_status
nvgpu_falcon_set_irq
nvgpu_falcon_copy_from_dmem
nvgpu_falcon_copy_from_imem
nvgpu_falcon_print_dmem
nvgpu_falcon_print_imem
nvgpu_falcon_get_ctls
nvgpu_falcon_dump_stats can be used in the safety debug build.
JIRA NVGPU-898
JIRA NVGPU-2214
Change-Id: Icb7f904b088aa74b976f75a6a0ecdb783486bab3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152978
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Rule 10.x necessitates operands to have essential type; left and right
operands are required to be of same width and type.
Rule 12.2 requires right hand operand of shift operator to be within
range 0 to 1 less than width of left hand operand.
Rule 20.7 requires macro parameters to be enclosed in parentheses.
This patch fixes above listed MISRA rule violations in
nvgpu/hal/fifo/ramin_gv11b_fusa.c.
Jira NVGPU-3821
Change-Id: I2d85cf8c4599e6d6f7bab1a2c3ce161d4ec93826
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153720
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Reduce code complexity of following functions in gr.config unit
gv100_gr_config_init_sm_id_table(complexity : 13)
gr_gv100_scg_estimate_perf(complexity : 23)
Create sub functions by moving the control statement codes
from the function which has high complexity above 10.
Create two sub functions from gv100_gr_config_init_sm_id_table function
gr_gv100_scg_estimate_perf_for_all_gpc_tpc(complexity : 5)
gv100_gr_config_set_sminfo(complexity : 3)
and reduce gv100_gr_config_init_sm_id_table complexity to 8
Create four sub functions from
gv100_gr_config_init_sm_id_table function
gr_gv100_find_max_gpc(with complexity : 2)
gr_gv100_remove_logical_tpc(with complexity : 4)
gr_gv100_calc_valid_pes(with complexity : 6)
gr_gv100_scg_calculate_perf(with complexity : 7)
and reduce gr_gv100_scg_estimate_perf complexity to 10
Jira NVGPU-3661
Change-Id: Iaaef1a98f2c6c55cd7b0a1a57d1c74eb09d43869
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156744
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reduce code complexity of following functions in gr.intr unit
gm20b_gr_intr_handle_exceptions(complexity : 13)
tu104_gr_intr_log_mme_exception(complexity : 13)
gv11b_gr_intr_handle_icache_exception(complexity : 17)
gv11b_gr_intr_handle_gpc_gpccs_exception(complexity : 13)
gv11b_gr_intr_handle_l1_tag_exception(complexity : 15)
gv11b_gr_intr_handle_gpc_gpcmmu_exception(complexity : 15)
Create sub functions by moving the control statement codes
from the function which has high complexity above 10.
Create following 8 sub functions for handling each exception from
gm20b_gr_intr_handle_exceptions function
gr_gm20b_intr_check_gr_fe_exception(complexity : 2)
gr_gm20b_intr_check_gr_memfmt_exception(complexity : 2)
gr_gm20b_intr_check_gr_pd_exception(complexity : 2)
gr_gm20b_intr_check_gr_scc_exception(complexity : 2)
gr_gm20b_intr_check_gr_ds_exception(complexity : 2)
gr_gm20b_intr_check_gr_ssync_exception(complexity : 4)
gr_gm20b_intr_check_gr_mme_exception(complexity : 3)
gr_gm20b_intr_check_gr_sked_exception(complexity : 2)
and reduce gm20b_gr_intr_handle_exceptions complexity to 3.
Create following 2 sub functions from tu104_gr_intr_log_mme_exception
function
gr_tu104_check_dma_exception(complexity : 6)
gr_tu104_check_ram_access_exception(complexity : 3)
and reduce tu104_gr_intr_log_mme_exception complexity to 6
Create following 2 sub functions for corrected and uncorrected error
reporting from gv11b_gr_intr_handle_icache_exception function
gv11b_gr_intr_report_icache_uncorrected_err(complexity : 5)
gv11b_gr_intr_report_icache_corrected_err(complexity : 5)
and reduce gv11b_gr_intr_handle_icache_exception complexity to 9
Create following 2 sub functions for corrected and uncorrected error
reporting from gv11b_gr_intr_handle_l1_tag_exception function
gv11b_gr_intr_report_l1_tag_uncorrected_err(complexity : 4)
gv11b_gr_intr_report_l1_tag_corrected_err(complexity : 4)
and reduce gv11b_gr_intr_handle_l1_tag_exception complexity to 9
Create following 1 sub function for error reporting from
gv11b_gr_intr_handle_gpc_gpccs_exception function
gv11b_gr_intr_report_gpccs_ecc_err(complexity : 5)
and reduce gv11b_gr_intr_handle_gpc_gpccs_exception complexity to 9
Create following 1 sub function for error reporting from
gv11b_gr_intr_handle_gpc_gpcmmu_exception function
gv11b_gr_intr_report_gpcmmu_ecc_err(complexity : 5)
and reduce gv11b_gr_intr_handle_gpc_gpcmmu_exception complexity to 9
Jira NVGPU-3661
Change-Id: I855b9ba055f3a8578c7b62cd59e249017ec31936
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155852
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Rule 8.6 requires each identifier with external linkage to have exactly
one external definitions.
Rule 10.x necessitates operands to have essential type; left and right
operands should be of same width and type.
This patch fixes above mentioned in nvgpu/hal/fifo/channel_gk20a.h,
nvgpu/hal/fifo/channel_gm20b.h and nvgpu/hal/fifo/channel_gv11b_fusa.c
Jira NVGPU-3827
Change-Id: I17a1d1bc4b04404b223f73e49330bf1a41d35129
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2154362
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Moved gv11b_fb_intr_inject_hubmmu_ecc_error from fb_intr_ecc_gv11b.c to
fusa version and deleted that file. Moved debugger related functions
from fb_gm20b.c to fusa version. Updated arch yaml to reflect the fusa
and non-fusa fb units.
JIRA NVGPU-3690
Change-Id: I929169e9aac62e8377e4ea7e8353caa970999299
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156879
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Moved gv11b_ltc_inject_ecc_error from ltc_gv11b to fusa version.
Moved debugger related functions from ltc_gm20b to fusa version.
Updated the arch yaml to reflect the non-fusa and fusa units
for ltc units.
JIRA NVGPU-3690
Change-Id: I48e360f18da760907e733023e013bd039ba5cca4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156878
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Moved debugger/cilp functions from gr ctxsw prog hal files for various
platforms to corresponding fusa files as currently they are enabled in
the safety build. Updated the arch yaml to reflect the non-fusa and
fusa units for gr ctxsw_prog.
JIRA NVGPU-3690
Change-Id: I188d3de223aa65816b5f511b776eb8278e221219
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156877
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA Advisory Rule 10.5 states that the value of an expression should
not be cast to an inappropriate essential type.
This change removes five violations of this rule that involve casting
boolean results to unsigned values:
* pass 1/0 (instead of true/false) to nvgpu_atomic operations
* fix skip_mask handling in gm20b_gr_init_pd_skip_table_gpc()
* fix l3_alloc flags check in nvgpu_gmmu_map_locked()
This change also eliminates several MISRA Advisory Rule 4.6 violations.
JIRA NVGPU-3798
Change-Id: I707da8a812bfb32eaeb2200463885c0961b197b3
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153070
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This patch adds SWUD (SW Unit Design) document for SDL unit. In addition,
it re-names err_type to err_id in error reporting APIs related to ECC, GR,
PRI and MMU, to keep the name consistent with other APIs.
JIRA NVGPU-3758
Change-Id: I968218574aa78144497fc12bd6dab20d1be7aa1c
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2151092
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
